1. Field of the Invention
The present invention relates to semiconductor memory, more particularly, to nonvolatile memory sensing circuits and techniques thereof which improve the reference structure therein.
2. Background of the Related Art
FIG. 1 shows a nonvolatile memory sensing circuit of two levels according to a related art, and FIG. 2 shows a nonvolatile memory sensing circuit of multi-levels according to a related art.
Referring to FIG. 1, a main cell array 110 including a main cell MC receives word line signals WL and selectively decodes the main cell. A voltage clamp 130 rapidly charges a bit line of the main cell MC and maintains fixed voltage therein. The voltage clamp 130 includes two transistors NM2 and NM3 of which drains are connected to applied voltage VCC and a sense amplifier 150 respectively, and an inverter INV1 which is connected commonly between sources and gates of the transistors NM2 and NM3. The inverter INV1 and NMOS transistor NM2 of which drain is connected to applied voltage VCC form a negative feed-back to the other NMOS transistor NM3 connecting the main cell to the sense amplifier 150, controlling drain voltage of another NMOS transistor NM1.
A reference cell controller 120 supplies a gate of a reference cell RFC with drain voltage Vd, control gate voltage Vcg, and erasing gate voltage Veg or erases them. Namely, outputs of an erasing decoder 125 and a program decoder 123 are outputted to a reference cell RFC through a cell erasing or program selection circuit 121. A reference cell array 140 having the reference cell RFC provides the sense amplifier 150 with the criteria judging the data stored in the main cell MC through an NMOS transistor NM4 of which gate receives clock signals.
The sense amplifier 150 which includes an NMOS transistor, PMOS transistors PM1 and PM2, and a latch pan 151 produces the result SA by comparing the levels of the reference cell RFC and main cell MC. Applied voltage VCC is applied to sources of the PMOS transistors PM1 and PM2 having a common gate. A drain and gate of the PMOS transistor PM1 are connected to the reference cell RFC in common while a drain of the other PMOS transistor PM2 is connected to the main cell MC and a stage of an NMOS transistor NM5 of which gate receives a clock signal. The latch part 151 connected to the other stage of the NMOS transistor NM5 outputs the result therefrom. The latch part 151 includes a pair of inverters INV2 and INV3 which form a feed-back structure. The sense amplifier 150, when the main cell MC is on the stage of reading operation, transforms the information of the reference cell RFC into reference voltage with the PMOS transistor PM1, then supplies the gate of the PMOS transistor PM2 with the reference voltage as gate voltage. Then, drain voltage of the PMOS transistor PM2 is transmitted to the latch part 151 through the NMOS transistor NM5 when the clock signal is at "high".
The operation of the nonvolatile memory sensing circuit of two levels of the related art is explained in the following description.
The cell controller 120 is in charge of the programming/erasing of the reference cell RFC in use of drain voltage Vd, control gate voltage Vcg, or erasing gate voltage Veg in accordance with each operational state. In read operation, once the clock signal CLK is enabled, the NMOS transistor NM4 is turned on. Thus, drain voltage of the PMOS transistor PM1 becomes reference voltage of the reference cell PFC since charges are transferred from applied voltage Vcc to the reference cell RFC. The same charges of the reference voltage applied to the gates of the PMOS transistors PM1 and PM2 of the sense amplifier 150 is also flown to the main cell MC because of the mirror phenomenon. In this case, the clock signal CLK is enabled and a read signal READ is applied. The NMOS transistor NM1 is turned on by receiving the word line signal WL to generate charge level of the main cell MC through the voltage clamp 130 to the sense amplifier 150. When the charge flown through the main cell MC is less than the reference charge, the voltage applied to a source of the NMOS transistor NM5 is recognized as `high level`. When the charge flown through the main cell MC is greater than the reference charge, the voltage applied to the source of the NMOS transistor NM5 is recognized as `low level`.
A drain voltage of the NMOS transistor NM1 is kept at fixed level by means of the fixed voltage clamp 130. Therefore, there is less chance that the main cell MC is exposed to bit line voltage and the sensitivity of the sense amplifier is increased to prevent the sensing operation being affected by the current variation of the main cell MC when the bit line is influenced by external factors on sensing. The result SA of the voltage level applied to the source of the NMOS transistor NM5 is outputted by the latch part 151.
FIG. 2 shows a nonvolatile memory sensing circuit of multi-levels according to a related art. Referring to FIG. 2, a main cell array 210 including a main cell MC receives word line signals ML and selectively decodes the main cell. A voltage clamp rapidly charges a bit line of the main cell MC and maintains a fixed voltage. A reference cell controller supplies a reference cell array with drain voltage Vd, control gate voltage Vcg, and erasing gate voltage Veg. A cell erasing and program selection circuit receiving an erasing signal Erase and programming signal Program which are decoded by an erasing decoder and programming decoder, which decode the erasing gate voltage Veg in accordance with the erasing or programming operation, supplies a reference cell array 240 with voltage of erasing or programming level. Various levels of a plurality of reference cells Refcell1 to Refcellk in the reference cell array 240 are applied to a sense amplifier 250 by the NMOS transistors N11 to N1k of which gates receive a plurality of clock signals CLK1 to CLKk, respectively.
The sense amplifier 250, which includes PMOS transistors P1 and P2, a plurality of NMOS transistors N21 to N2k, and a plurality of latch parts, outputs the results SA1 to SAk by comparing the multi level of the reference cell array 250 to the level of the main cell MC. Applied voltage VCC is connected to sources of the PMOS transistors P1 and P2 which share a gate in common. A drain of the PMOS transistor P1 and the common gate are connected to a reference cell. A drain of the other PMOS transistor is connected to the main cell as well as a plurality of the NMOS transistors N21 to N2k of which gates receive a plurality of clock signals CLK1 to CLKk in parallel.
A plurality of latch parts connected to the other ends of the NMOS transistors N21 to N2k, respectively, produce the results SA1 to SAk. Each of the latch parts includes a pair of inverters forming a feed-back structure. The decoder 260 outputs the final values Bit1 to BitL by decoding the results SA1 to SAk produced by the sense amplifier 250. The nonvolatile memory sensing circuit of multi-levels according to the related art shows the same operation as that of the circuit of two levels, except for having the reference cell array 240 consist of a plurality of reference cells Ref Cell1 to Ref Cellk and programming various k number of reference voltages to sense the multi-levels of k+1.
In reading operation, when a plurality of the clock signals CLK1 to CLKk are enabled in order, the sense amplifier 250 supplied with charge levels of a plurality of the reference cells Refcell1 to Refcellk and the main cell MC stores the results in a plurality of the latch parts 241, 243, 245, by comparing the multi-levels of the reference cell array 240 to the level of the main cell MC. After the operations by the clock signals CLK1 to CLKk have been completed successively, the results SA1 to SAk are produced to the decoder 260. Then, the decoder 260 outputs the final values Bit1 to BitL by judging the data of the main cell MC by decoding the results SA1 to SAk outputted by the sense amplifier 250.
Unfortunately, both of the memory sensing circuits of two and multi-levels according to the related art require an additional controller such as program control means and read control means for the main and reference cell programs and for reading the main or reference cell. When the reference cell is programmed in use of a programming means, voltage offset of the programming means occurs. The voltage offset is caused by the variations of fabrication due to temperature, pressure, and the like. Thus, voltage offset of the program controller is inevitable when the reference cell is programmed.
Moreover, the sensing margin is decreased by the influence on the reference cell due to the voltage offset of the reading control means when the reference cell is read by the reading control means, thereby causing the direct fail in the precise reading operation of the memory sensing circuit of multi-levels of which reading margin is basically less than that of two levels.